PIC16F87X
FIGURE 11-1: A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
100
V
AIN
(Input voltage)
011
010
A/D
Converter
001
RE2/AN7
(1)
RE1/AN6
(1)
RE0/AN5
(1)
RA5/AN4
RA3/AN3/V
REF
+
RA2/AN2/V
REF
-
RA1/AN1
V
DD
V
REF
+
(Reference
voltage)
PCFG3:PCFG0
000
RA0/AN0
V
REF
-
(Reference
voltage)
V
SS
PCFG3:PCFG0
Note 1:
Not available on 28-pin devices.
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD
) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The
source impedance (R
S
) and the internal sampling
switch (R
SS
) impedance directly affect the time
required to charge the capacitor C
HOLD
. The sampling
switch (R
SS
) impedance varies over the device voltage
(V
DD
), Figure 11-2.
The maximum recommended
impedance for analog sources is 10 kΩ.
As the
impedance is decreased, the acquisition time may be
decreased. After the analog input channel is selected
(changed), this acquisition must be done before the
conversion can be started.
To calculate the minimum acquisition time,
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, T
ACQ
, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
DS30292B-page 114
©
1999 Microchip Technology Inc.
ETC [ ETC ]
