PIC16F87X
FIGURE 15-20: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(1)
(TOSC/2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP
instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
Standard(F)
Extended(LF)
Standard(F)
Extended(LF)
130
TAD A/D clock period
1.6
3.0
2.0
3.0
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
TOSC based, VREF ≥ 2.0V
4.0
6.0
—
6.0
9.0
12
µs A/D RC Mode
µs A/D RC Mode
TAD
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
Note 2
10*
40
—
—
—
µs
µs The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for min conditions.
1999 Microchip Technology Inc.
DS30292B-page 171
ETC [ ETC ]
