PIC16F87X
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
R/W-0
R-0
R-0
R-x
RX9D
bit0
CREN ADDEN
FERR
OERR
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3:
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1= Enables address detection, enable interrupt and load of the receive burffer when RSR<8> is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2:
bit 1:
bit 0:
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data (Can be parity bit)
DS30292B-page 96
1999 Microchip Technology Inc.
ETC [ ETC ]
