PIC16F87X
2
example, with a supply voltage of VDD = 5V+10% and
9.3
Connection Considerations for I C
Bus
VOL max = 0.4V at 3 mA, R
= (5.5-0.4)/0.003 =
p min
1.7 kΩ. VDD as a function of R is shown in Figure 9-27.
p
2
For standard-mode I C bus devices, the values of
The desired noise margin of 0.1VDD for the low level
resistors R and R in Figure 9-27 depend on the fol-
limits the maximum value of R . Series resistors are
p
s
s
lowing parameters:
optional and used to improve ESD susceptibility.
• Supply voltage
• Bus capacitance
The bus capacitance is the total capacitance of wire,
connections, and pins. This capacitance limits the max-
• Number of connected devices
(input current + leakage current).
imum value of R due to the specified rise time
(Figure 9-27).
p
The supply voltage limits the minimum value of resistor
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I C mode (master or slave).
R
due to the specified minimum sink current of 3 mA
p
2
at VOL max = 0.4V for the specified output stages. For
2
FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I C BUS
VDD + 10%
DEVICE
Rp
Rp
Rs
Rs
SDA
SCL
Cb=10 - 400 pF
Note:
I2C devices with input levels related to VDD must have one common supply
line to which the pull-up resistor is also connected.
1999 Microchip Technology Inc.
DS30292B-page 93
ETC [ ETC ]
