PIC16F87X
TABLE 2-1:
Addres
s
Bank 2
100h
(4)
101h
102h
(4)
(4)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
0000 0000
Name
INDF
TMR0
PCL
STATUS
FSR
—
PORTB
—
—
—
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
—
—
—
—
—
—
—
—
103h
104h
(4)
105h
106h
107h
108h
109h
10Ah
(1,4)
10Bh
(4)
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
(4)
181h
182h
(4)
183h
(4)
184h
(4)
185h
186h
187h
188h
189h
18Ah
(1,4)
18Bh
(4)
18Ch
18Dh
18Eh
18Fh
Indirect data memory address pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
GIE
—
PEIE
—
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
EEPROM data register
EEPROM address register
—
—
—
—
EEPROM data register high byte
—
EEPROM address register high byte
INDF
OPTION_R
EG
PCL
STATUS
FSR
—
TRISB
—
—
—
PCLATH
INTCON
EECON1
EECON2
—
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
—
—
—
—
—
—
—
—
Indirect data memory address pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
—
GIE
EEPGD
—
PEIE
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
INTE
—
RBIE
WRERR
T0IF
WREN
INTF
WR
RBIF
RD
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
x--- x000 x--- u000
---- ---- ---- ----
0000 0000 0000 0000
0000 0000 0000 0000
EEPROM control register2 (not a physical register)
Reserved maintain clear
Reserved maintain clear
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6:
PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
©
1999 Microchip Technology Inc.
DS30292B-page 17
ETC [ ETC ]
