PIC16F873-04ISO 参数 Datasheet PDF下载

PIC16F87X

TABLE 2-1:

Addres

s

Bank 1

80h

(4)

81h

82h

(4)

83h

(4)

84h

(4)

85h

86h

87h

88h

(5)

89h

(5)

8Ah

(1,4)

8Bh

(4)

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

INDF

OPTION_R

EG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

TRISD

TRISE

PCLATH

INTCON

PIE1

PIE2

PCON

—

—

SSPCON2

PR2

SSPADD

SSPSTAT

—

—

—

TXSTA

SPBRG

—

—

—

—

ADRESL

ADCON1

Addressing this location uses contents of FSR to address data memory (not a physical register)

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

PD

Z

DC

C

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--11 1111 --11 1111

1111 1111 1111 1111

1111 1111 1111 1111

1111 1111 1111 1111

PSPMODE

—

PORTE Data Direction Bits

0000 -111 0000 -111

---0 0000 ---0 0000

0000 000x 0000 000u

0000 0000 0000 0000

-r-0 0--0 -r-0 0--0

---- --qq ---- --uu

—

—

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

—

—

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(2)

Name

Program Counter’s (PC) Least Significant Byte

IRP

RP1

RP0

TO

Indirect data memory address pointer

—

—

PORTA Data Direction Register

PORTB Data Direction Register

PORTC Data Direction Register

PORTD Data Direction Register

IBF

—

GIE

PSPIE

—

—

Unimplemented

Unimplemented

GCEN

ACKSTAT

Timer2 Period Register

Synchronous Serial Port (I

2

C mode) Address Register

SMP

CKE

D/A

P

S

R/W

UA

BF

Unimplemented

Unimplemented

Unimplemented

CSRC

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

Baud Rate Generator Register

Unimplemented

Unimplemented

Unimplemented

Unimplemented

A/D Result Register Low Byte

ADFM

—

—

—

PCFG3

PCFG2

PCFG1

PCFG0

(3)

OBF

—

PEIE

ADIE

(6)

—

IBOV

—

T0IE

RCIE

—

—

Write Buffer for the upper 5 bits of the Program Counter

INTE

TXIE

EEIE

—

RBIE

SSPIE

BCLIE

—

T0IF

CCP1IE

—

—

INTF

TMR2IE

—

POR

RBIF

TMR1IE

CCP2IE

BOR

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0000

—

—

—

—

—

—

0000 -010 0000 -010

0000 0000 0000 0000

—

—

—

—

0--- 0000

—

—

—

—

0--- 0000

xxxx xxxx uuuu uuuu

Legend:

x

= unknown,

u

= unchanged,

q

= value depends on condition, - = unimplemented read as ’0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1:

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2:

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3:

Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

4:

These registers can be addressed from any bank.

5:

PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.

6:

PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

DS30292B-page 16

©

1999 Microchip Technology Inc.