T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT350
Table 24. DC Electrical Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions
Digital I/O pins
High level input voltage 1,2 (pins 1-4, 23-25)4
Low level input voltage 1,2 (pins 1-4, 23-25)4
High level output voltage 1,2 (pins 6-8, 12, 23, 25)4
Low level output voltage 1,2 (pins 6-8, 12, 23, 25)4
Tri-state leakage current 1 (all outputs)
VIH
2.0
–
–
–
–
–
–
–
0.8
–
V
V
VIL
VOH
2.4
–
V
IOUT = -400 µA
VOL
0.4
±10
V
IOUT = 1.6 mA
I3L
Mode input pins
VIH
0
µA
High level input voltage 3 (pins 5, 9, 11, 26-28)4
Midrange output voltage 3 (pins 5, 9, 11, 26-28)4
3.5
2.3
–
–
–
V
V
VOM
2.7
Host Mode
H/W Mode
VIL
VIL
–
–
–
–
0.8
1.5
V
V
Low level input voltage 3 (pins 5, 9, 11, 26-28)4
Input leakage current (pins 5, 9, 11, 26-28)4
Tri-state leakage current1 (all outputs)
ILL
0
0
–
–
±50
±10
µA
µA
I3L
In power down
and tristate
TTIP/TRING leakage current
ITR
–
–
1.2
mA
1. Functionality of pin 23 and 25 depends on mode. See Host mode and Hardware mode description.
2. Output drivers will output CMOS logic levels into CMOS loads.
3. As an alternative to supplying 2.3 - 2.7 V to these pins, they may be left open.
4. Listed pins are for the PLCC package. Refer to “Pin Assignments and Signal Descriptions” on page 8 for the 44-pin QFP
package.
Table 25. Analog Characteristics
Parameter
Min
Typ1
Max
Unit
Test Conditions
Recommended output load on TTIP/TRING
50
2.4
2.7
–
–
3.0
3.0
–
200
3.6
Ω
V
T1
RL = 100 Ω
RL = 120 Ω
AMI output pulse amplitudes
E1
3.3
V
10 Hz - 8 kHz 3
8 kHz - 40 kHz 3
10 Hz - 40 kHz3
Broad Band
0.02
0.025
0.025
0.05
UI
UI
UI
UI
–
–
Jitter added by the
transmitter2
–
–
–
–
@ 1024 kHz
1.431
Receiver sensitivity
0
–
18
dB
Allowable consecutive zeros before LOS (T1)
Allowable consecutive zeros before LOS (E1)
160
–
175
32
–
190
–
–
–
10 kHz - 100 kHz
1 Hz3
0.4
138
–
UI
UI
0 dB line
AT&T Pub 62411
Input jitter tolerance (T1)
–
–
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.
3. Guaranteed by characterization; not subject to production testing.
4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
Datasheet
39
ETC [ ETC ]
