HT48R50A-1/HT48C50-1
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a
²warm
reset². After the TO and PD flags are ex-
amined, the reason for chip reset can be determined.
The PD flag is cleared by system power-up or executing
the
²CLR
WDT² instruction and is set when executing
the
²HALT²
instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others remain in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
²1²
before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
SYS
(system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The RTC oscillator still runs in the HALT mode (if the
RTC oscillator is enabled).
Reset
There are three ways in which a reset can occur:
·
RES reset during normal operation
·
RES reset during HALT
·
WDT time-out reset during normal operation
V D D
R E S
S S T T im e - o u t
C h ip
R e s e t
t
S
S T
Reset timing chart
H A L T
W D T
R E S
W a rm
R e s e t
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
C o ld
R e s e t
Reset configuration
tions are met. By examining the PD and TO flags, the
program can distinguish between different
²chip
resets².
TO
0
u
0
1
1
PD
0
u
1
u
1
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Note:
²u²
stands for
²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
PC
Interrupt
Prescaler
WDT
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a
²warm
re -
set² that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the
²initial
condition² when the reset condi-
V
D D
R E S
Timer/Event Counter
Input/Output Ports
SP
Reset circuit
Rev. 1.00
13
January 2, 2003
ETC [ ETC ]
