HT48R50A-1/HT48C50-1
OSC1 and OSC2 are required. If the internal RC oscilla-
tor is used, the OSC1 and OSC2 can be selected as
general I/O lines or an 32768Hz crystal oscillator (RTC
OSC). Also, the frequencies of the internal RC oscillator
can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (depends
on the options).
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 78ms. The WDT oscillator can be disabled by options to
conserve power.
Watchdog Timer
-
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), RTC clock or instruction
clock (system clock divided by 4), determines the op-
tions. This timer is designed to prevent a software mal-
function or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by options. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation. The RTC clock is enabled only in the in-
ternal RC+RTC mode.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
16.6ms/5V. This time-out period may vary with tempera-
tures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)
can give different time-out periods. If WS2, WS1, and
WS0 are all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.2s/5V seconds. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are re-
served for user's defined flags, which can be used to in-
dicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla-
tor (RTC OSC) is strongly recommended, since the HALT
will stop the system clock.
S y s te m
R T C
C lo c k /4
O S C
W D T
O S C
W D T P r e s c a le r
O p tio n
S e le c t
8 - b it C o u n te r
7 - b it C o u n te r
WS2
0
0
0
0
1
1
1
1
WS1
0
0
1
1
0
0
1
1
WS0
0
1
0
1
0
1
0
1
WDTS register
Division Ratio
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
The WDT overflow under normal operation will initialize
²chip
reset² and set the status bit
²TO².
But in the HALT
mode, the overflow will initialize a
²warm
reset² and only
the PC and SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three methods are
adopted; external reset (a low level to RES), software in-
struction and a
²HALT²
instruction. The software instruc-
tion include
²CLR
WDT² and the other set
- ²CLR
WDT1² and
²CLR
WDT2². Of these two types of instruc-
tion, only one can be active depending on the option
-
²CLR
WDT times selection option². If the
²CLR
WDT² is
selected (i.e. CLRWDT times equal one), any execution
of the
²CLR
WDT² instruction will clear the WDT. In the
case that
²CLR
WDT1² and
²CLR
WDT2² are chosen
(i.e. CLRWDT times equal two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power down operation
-
HALT
The HALT mode is initialized by the
²HALT²
instruction
and results in the following...
·
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
·
The contents of the on chip RAM and registers remain
unchanged.
·
WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
·
All of the I/O ports maintain their original status.
·
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
8 -to -1 M U X
W D T T im e - o u t
W S 0 ~ W S 2
Watchdog Timer
Rev. 1.00
12
January 2, 2003
ETC [ ETC ]
