CR6853
circuit in the CR6853 to improve the
credibility and extend the life of the chip.
When the VDD voltage is over 34V, the
GATE pin is to shutdown immediately and
the VDD voltage is to descend rapidly.
Anti Intermission Surge
When the power supplies change the
heavy load to light load immediately, there
could be tow phenomena caused by system
delay. They are output voltage overshot and
intermission surge. To avoid it, the anti
intermission surge is built in the CR6853. If it
occurs, the FB current is to increase rapidly,
the GATE would be cut off for a while, VDD
pin voltage descends gradually. When VDD
reaches 9.4V, the GATE pin would operate
again, which the frequency is 22KHz.
GATE Driver & Soft Clamped
The CR6853’ output designs a totem
pole to drive a periphery power MOSFET.
The dead time is introduced to minimize the
transfixion current during the output
operating. The novel soft clamp technology
is introduced to protect the periphery power
MOSFET from breaking down and current
saturation of the Zener.
Leading-edge Blanking (LEB)
Each time the power MOSFET is
switched on, a turn-on spike will inevitably
occur at the Sense pin, which would disturb
the internal signal from the sampling of the
RSENSE. There is a 300nS leading edge
blanking time built in to avoid the effect of
the turn-on spike, and the power MOSFET
cannot be switched off during the moment.
So that the conventional external RC
filtering on sense input is no longer required.
Low EMI technique
The frequency low EMI technique is
introduced in the CR6853. As following
figure, the internal oscillation frequency is
modulated by itself. A whole surge cycle
includes 128 pulses and the jittering ranges
from -4% to +4%. Thus, the function could
minimize the electromagnetic interferer from
the power supply module.
Frequency(HZ)
70K
65K
60K
Time
Frequency low EMI
Over Voltage Protection (OVP)
There is a 34V over-voltage protection
Oct, 2008 V2.0
8/12
Chengdu Chip-Rail Tech. Co., Ltd.
http://www.chiprail.com
ETC [ ETC ]
