PIC18FXX2
FIGURE 1-2:
PIC18F4X2 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
Table Pointer
Data Latch
21
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Data RAM
(up to 4K
address reach)
8
8
8
inc/dec logic
21
21
Address Latch
12(2)
PCLATU
PCLATH
Address Latch
Program Memory
(up to 2 Mbytes)
Address<12>
PCH PCL
Program Counter
PCU
PORTB
4
BSR
12
4
Data Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
RB4
Bank0, F
FSR0
FSR1
FSR2
31 Level Stack
12
RB5/PGM
RB6/PCG
RB7/PGD
16
inc/dec
logic
Decode
Table Latch
8
ROM Latch
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
Instruction
Register
8
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
OSC2/CLKO
OSC1/CLKI
3
Power-up
Timer
PORTD
8
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Timing
Generation
Oscillator
Start-up Timer
WREG
8
T1OSCI
T1OSCO
BIT OP
8
8
Power-on
Reset
8
Watchdog
Timer
4X PLL
ALU<8>
Brown-out
Reset
8
Precision
Voltage
Reference
PORTE
Low Voltage
Programming
MCLR
RE0/AN5/RD
In-Circuit
Debugger
RE1/AN6/WR
RE2/AN7/CS
VDD, VSS
A/D Converter
Timer0
CCP1
Timer1
CCP2
Timer2
Timer3
Master
Synchronous
Serial Port
Addressable
USART
Parallel Slave Port
Data EEPROM
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
2002 Microchip Technology Inc.
DS39564B-page 9
ETC [ ETC ]
