I90135
Product Data Sheet
Version 1.2 (June 1999)
The demapper converts the constellation
points computed by the FFT to a block of
bits. This essentially consists in identifying
a point in a 2D QAM constellation plane.
The demapper supports trellis coded
demodulation and provides a Viterbi
maximum likelihood estimator. When the
trellis is active, the demapper receives an
indication for the most likely constellation
subset to be used. In the transmit
direction, the mapper performs the inverse
operation, mapping a block of bits into one
Mapper/Demapper, Monitor, Trellis
Coding, FEQ Update
constellation point (in a complex x+jy
representation) which is passed to the IFFT
block. The Trellis Encoder generates
redundant bits to improve the robustness of
the transmission, using a 4-Dimensional
Trellis Coded Modulation scheme. The
Monitor computes error parameters for
carriers specified in the Demapper process.
Those parameters can be used for updates
of adaptive filters coefficient, clock phase
adjustments, error detection, etc. A series
of values is constantly monitored, such as
signal power, pilot phase deviations, symbol
erasures generation, loss of frame, etc.
Pin Diagram
AFTXD_3
VDD
143
144
AFTXD_2
142
AFTXD_1
VSS
140
141
AFTXD_0
139
VDD
IDDQ
137
138
AFTXED_3
136
VSS
AFTXED_2
134
135
AFTXED_1
133
VDD
AFTXED_0
131
132
CTRLDATA
130
CLWD
MCLK
128
129
VSS
127
AFRXD_2
AFRXD_3
125
126
AFRXD_1
124
VDD
AFRXD_0
122
123
GP_OUT
PDOWN
120
121
TESTSE
119
VSS
TRSTB
117
118
TCK
116
TMS
VDD
114
115
TDO
113
SLT_FRAME_S 111
TDI
112
SLT_REQ_S
110
VSS
109
VSS
AD_0
AD_1
AD_2
VDD
AD_3
AD_4
VSS
AD_5
AD_6
VDD
AD_7
AD_8
AD_9
VSS
AD_10
AD_11
VDD
AD_12
VSS
PCLK
VDD
AD_13
AD_14
AD_15
VSS
BE1
ALE
VDD
CSB
WR_RDB
RDYB
OBC_TYPE
INTB
RESETB
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
38
37
U_RXDATA_0
VDD
39
U_RXDATA_1
41
40
U_RXDATA_2
VSS
42
U_RXDATA_3
44
43
U_RXDATA_4
VDD
45
47
46
48
50 U_RX_ADDR_0
49
VDD
51 U_RX_ADDR_1
53 U_RX_ADDR_3
52 U_RX_ADDR_2
54
56
GP_IN_0
55 U_RX_ADDR_4
57
59
58
61
60
62
64
63
65
67
66
68
70
69
71
72
108
107
106
105
104
103
102
VDD
SLT_REQ_F
SLT_DAT_S0
SLT_DAT_S1
SLT_DAT_F0
SLT_DAT_F1
VSS
AFE
TEST
SLAP
101 SLT_FRAME_F
100 SLAP_CLOCK
99
SLR_VAL_F
98
97
96
95
94
93
SLR_DAT_F0
SLR_DAT_F1
SLR_VAL_S
VDD
SLR_DAT_S0
SLR_DAT_S1
OBC
92 SLR_FRAME_S
91
VSS
90 SLR_FRAME_F
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
U_TX_ADDR_0
U_TX_ADDR_1
U_TX_ADDR_2
VDD
U_TX_ADDR_3
U_TX_ADDR_4
U_TX_DATA_0
U_TX_DATA_1
VDD
U_TX_DATA_2
U_TX_DATA_3
U_TX_DATA_4
U_TX_DATA_5
VDD
U_TX_DATA_6
U_TX_DATA_7
VSS
UTOPIA
Figure 3: Pinout (Topside View)
U_RXDATA_5
U_RXDATA_6
VSS
U_RXDATA_7
U_RX_REFB
U_TX_REFB
U_RX_CLAV
U_TX_CLAV
U_TXSOC
VSS
U_RXENBB
U_TXENBB
U_RXSOC
U_RXCLK
U_TXCLK
VSS
GP_IN_1
VDD
VDD
VDD
VSS
Integrated Telecom Express, Inc.
5
ETC [ ETC ]
