Data Sheet
June 1999
ORCA Series 2 FPGAs
Pin Information (continued)
Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B
256-Pin PBGA Pinout (continued)
Pin
Function
2C/2T06A Pad
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
2C/2T08A Pad
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
2C/2T10A Pad
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
2C/2T12A Pad
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
2C/2T15A/B Pad
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
U8
U13
U17
B1
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D6
D11
D15
F4
F17
K4
L17
R4
R17
U6
U10
U15
W3
J10
J11
J12
J9
K10
K11
K12
K9
L10
L11
L12
L9
M10
M11
M12
M9
No Connect
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS—ETC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Notes:
The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table.
The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17.
The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series.
The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground
plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected.
98
Lucent Technologies Inc.
ETC [ ETC ]
