Specifications
ispLSI 2064/A
ispLSI 2064/A Timing Model
I/O Cell
GRP
Feedback
Ded. In
Comb 4 PT Bypass #23
GRP
#22
Reg 4 PT Bypass
#24
20 PT
XOR Delays
#25, 26, 27
Reset
#45
D
RST
#29, 30,
31, 32
GLB Reg Bypass
#28
GLB Reg
Delay
Q
ORP Bypass
#37
ORP
Delay
#36
#38,
39
I/O Pin
(Output)
GLB
ORP
I/O Cell
#21
I/O Delay
#20
Y0,1,2
GOE 0,1
#43, 44
#42
EW
N
Control RE
PTs
OE
#33, 34, CK
35
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
su
=
=
=
3.5 ns =
=
=
=
2.6 ns =
=
=
=
9.4 ns =
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
Table 2- 0042A-2064
t
h
t
co
U
SE
is
Note: Calculations are based upon timing specifications for the ispLSI 2064/A-125L.
pL
SI
2
06
4E
FO
7
R
D
ES
IG
#40, 41
0491/2064
N
S
I/O Pin
(Input)
ETC [ ETC ]
