ISPLSI2064A-100LJ84 参数 Datasheet PDF下载

型号：	ISPLSI2064A-100LJ84
PDF下载：	下载PDF文件查看货源
内容描述：	电可擦除可编程逻辑器件复杂\n [Electrically-Erasable Complex PLD ]
分类和应用：	可编程逻辑器件
文件页数/大小：	13 页 / 164 K
品牌：	ETC [ ETC ]

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Specifications

ispLSI 2064/A

Functional Block Diagram

Figure 1. ispLSI 2064/A Functional Block Diagram

GOE 0

GOE 1

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

Input Bus

Generic Logic

Blocks (GLBs)

Megablock

Output Routing Pool (ORP)

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

SDI/IN 0

MODE/IN 1

Input Bus

I/O 4

I/O 5

I/O 6

I/O 7

Output Routing Pool (ORP)

I/O 0

I/O 1

I/O 2

I/O 3

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

SCLK/IN 3

SDO/IN 2

Global Routing Pool

(GRP)

ispEN

Input Bus

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

The devices also have 64 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

individually programmed to be a combinatorial input,

output or bi-directional I/O pin with 3-state control. The

signal levels are TTL compatible voltages and the output

drivers can source 4 mA or sink 8 mA. Each output can

be programmed independently for fast or slow output

slew rate to minimize overall output switching noise.

Eight GLBs, 32 I/O cells, two dedicated inputs and two

ORPs are connected together to make a Megablock

(Figure 1). The outputs of the eight GLBs are connected

to a set of 32 universal I/O cells by two ORPs. Each ispLSI

2064 and 2064A device contains two Megablocks.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2064 and 2064A devices are se-

lected using the dedicated clock pins. Three dedicated

clock pins (Y0, Y1, Y2) or an asynchronous clock can be

selected on a GLB basis. The asynchronous or Product

Term clock can be generated in any GLB for its own clock.

CLK 0

CLK 1

CLK 2

0139B(1)isp/2064

RESET

Output Routing Pool (ORP)

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