HT1625
Functional Description
Display memory
-
RAM structure
The static display RAM is organized into 128´4 bits and
stores the display data. The contents of the RAM are di-
rectly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The following is a
mapping from the RAM to the LCD patterns.
Time base and Watchdog Timer
-
WDT
The time base generator and WDT share the same di-
vided (/256) counter. TIMER DIS/EN/CLR
, WDT DIS/EN/CLR and IRQ EN/DIS are independent
from each other. Once the WDT time-out occurs, the
IRQ pin will remain at logic low level until the CLR WDT
or the IRQ DIS command is issued.
C O M 7
S E G 0
S E G 1
S E G 2
S E G 3
7
5
6
3
4
A d d r e s s 7 B its
(A 6 , A 5 , ...., A 0 )
C O M 6
C O M 5
C O M 4
1
2
C O M 3
If an external clock is selected as the source of system
frequency, the SYS DIS command turns out invalid and
the power down mode fails to be carried out until the ex-
ternal clock source is removed.
Buzzer tone output
A simple tone generator is implemented in the HT1625.
The tone generator can output a pair of differential driv-
ing signals on the BZ and BZ which are used to generate
a single tone.
Command format
The HT1625 can be configured by the software setting.
There are two mode commands to configure the
HT1625 resource and to transfer the LCD display data.
C O M 2
C O M 1
C O M 0
0
S E G 6 3
D 3
D 2
D 1
D 0
1 2 7
A d d r
D a ta
D 3
D 2
D 1
D 0
1 2 6
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
T im e B a s e
C lo c k S o u r c e
/2 5 6
V
C L R
T im e r
D D
T IM E R
E N /D IS
IR Q
W D T E N /D IS
D
C K
R
Q
IR Q
E N /D IS
W D T
/4
C L R
W D T
Timer and WDT configurations
Rev. 1.10
8
September 11, 2002
ETC [ ETC ]
