HT1625
Pad Assignment
S E G 6 1
S E G 6 0
S E G 5 9
S E G 5 8
S E G 5 7
S E G 5 6
S E G 5 5
S E G 5 4
S E G 5 3
S E G 5 2
S E G 5 1
S E G 5 0
S E G 4 9
S E G 4 8
S E G 4 7
S E G 4 6
S E G 4 5
S E G 4 4
S E G 4 3
S E G 6 3
S E G 6 2
C S
R D
W R
D A T A
V S S
3
1
2
4
8 7 8 6 8 5 8 4 8 3 8 2
8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1
7 0
6 9 6 8
6 7 6 6
6 5
6 4
6 3
6 2
S E G 4 2
S E G 4 1
S E G 4 0
S E G 3 9
S E G 3 8
S E G 3 7
S E G 3 6
S E G 3 5
S E G 3 4
S E G 3 3
S E G 3 2
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 0
O S C I
O S C O
V D D
V L C D
8
9
IR Q
B Z
B Z
T 1
T 2
T 3
C O M 0
C O M 1
C O M 2
C O M 3
7
6
5
6 1
6 0
5 9
5 8
5 7
5 6
(0 , 0 )
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
C O M 4
1 9
2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7
C O M 5
C O M 6
C O M 7
S E G 0
S E G 1
S E G 2
S E G 3
S E G 4
S E G 5
S E G 6
S E G 7
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
3 8 3 9
S E G 1 5
S E G 1 6
4 0 4 1
S E G 1 7
S E G 1 8
4 2
S E G 1 9
4 4
4 3
Chip size: 192
´
211 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.10
3
September 11, 2002
ETC [ ETC ]
