Chapter 2 Function Block
Chapter 2 Function Block
Switching speed
D-F/F with R
Function
Block
type
Input
Output
Path
→
t LD0 (ns)
t 1
Standard type
Low Gate type
Block type
IN
OUT
MIN.
TYP. MAX.
MIN.
0.011
0.010
0.011
0.010
0.010
0.011
TYP. MAX. Symbol Fanin Symbol Fanout
Normal
Q output
QB output
Normal
Q output
QB output
(HH) 0.374
(HL) 0.404
(HH) 0.498
(HL) 0.583
(HL) 0.357
(HH) 0.184
0.610
0.570
0.655
0.823
0.933
0.602
0.334
1.029
1.214
1.568
1.718
1.126
0.579
1.720
0.310
1.230
0.290
2.113
1.597
1.029
1.213
1.046
1.720
0.310
1.230
0.290
1.586
1.491
0.993
1.039
0.817
1.590
0.310
1.120
0.250
1.429
1.298
0.015
0.013
0.015
0.013
0.013
0.015
0.022
0.017
0.021
0.019
0.017
0.022
D
C
R
1.0
1.0
2.2
Q
35
34
F642
C
C
→
Q
Drivability
Name cells
Name cells
Name cells
Name cells
Name cells
Name cells
QB
→
QB
Low Power
F642
9
F642NQ
8
F642NB
8
x1
x2
x4
R
R
→
→
Q
QB
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
C
R
0.380
0.400
0.410
0.788
Logic Diagram for "Normal"
Truth Table for "Normal"
D
C
R
Q
QB
D
C
H01
H02
N01
Q
Min Pulse
0.585
(HH) 0.373
(HL) 0.401
(HL) 0.335
0.610
0.570
0.652
0.561
0.011
0.010
0.010
0.015
0.013
0.013
0.022
0.017
0.017
D
C
R
1.0
1.0
2.2
Q
35
F642NQ
C
→
Q
Q
0
1
0
0
0
1
0
1
1
0
R
→
X
X
Hold
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
C
R
N02 QB
0.380
0.400
0.410
0.578
X
0
1
X:Irrelevant
H03
R
Min Pulse
0.529
(HH) 0.331
(HL) 0.361
(HH) 0.264
0.610
0.532
0.576
0.434
0.011
0.011
0.011
0.015
0.015
0.015
0.022
0.022
0.022
D
C
R
1.0
1.0
2.2
QB
34
F642NB
C
→
QB
QB
R
→
Logic Diagram for "Q output"
Set up time
Hold time
Release time
Removal time
Min Pulse
D
D
R
R
C
R
Truth Table for "Q output"
0.390
0.410
0.390
0.558
D
C
R
Q
D
C
H01
H02
N01
Q
0
1
0
0
0
1
0
1
Min Pulse
0.500
X
X
Hold
0
X
X:Irrelevant
H03
R
Logic Diagram for "QB output"
Truth Table for "QB output"
D
C
R
QB
D
C
H01
H02
0
1
0
0
0
1
1
0
X
X
Hold
1
N01 QB
X
X:Irrelevant
H03
R
Block Library A13872EJ5V0BL
2 - 266
Block Library A13872EJ5V0BL
2 - 267
ETC [ ETC ]
