3.1.3 Estimated Wiring Capacitance
The values of estimated wiring capacitance (converted to Fan-in mode) of CMOS-N5 family are shown in
the table below.
(1/2)
Master
Pin Pairs
1
2
3
4
5
6
µ PD65880
1.621
1.641
1.684
1.730
1.757
1.780
1.819
1.861
1.904
1.943
3.266
3.356
3.552
3.767
3.892
3.997
4.175
4.372
4.569
4.747
4.911
5.070
5.421
5.803
6.026
6.213
6.532
6.883
7.233
7.552
6.556
6.785
7.289
7.840
8.161
8.430
8.889
9.393
9.897
10.356
8.200
8.500
9.845
10.214
11.027
11.913
12.430
12.863
13.602
14.414
15.226
15.965
µ PD65881
µ PD65882
µ PD65883
µ PD65884
µ PD65885
µ PD65887
µ PD65889
µ PD65890
µ PD65893
9.158
9.876
10.295
10.647
11.245
11.904
12.562
13.160
(2/2)
Master
Pin Pairs
7
8
9
10
11 to 15 16 to 20
µ PD65880
µ PD65881
µ PD65882
µ PD65883
µ PD65884
µ PD65885
µ PD65887
µ PD65889
µ PD65890
µ PD65893
11.490
11.929
12.895
13.949
14.564
15.080
15.958
16.925
17.891
18.769
13.135
13.644
14.764
15.986
16.699
17.297
18.315
19.435
20.555
21.574
14.779
15.358
16.632
18.022
18.833
19.513
20.672
21.946
23.220
24.378
16.424
17.073
18.501
20.059
20.967
21.730
23.028
24.456
25.884
27.182
24.648
25.647
27.844
30.241
31.640
32.813
34.811
37.009
39.206
41.204
32.871
34.220
37.187
40.424
42.312
43.897
46.594
49.561
52.528
55.226
Preface-4
Block Library A13872EJ5V0BL
ETC [ ETC ]
