IEGR—IRQ edge select register
H'F2
System control
Bit
7
—
0
6
—
1
5
—
1
4
IEG4
0
3
IEG3
0
2
IEG2
0
1
0
IEG1
0
IEG0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
IRQ0 edge select
0
1
Falling edge of IRQ0 pin input is detected
Rising edge of IRQ0 pin input is detected
IRQ1 edge select
0
1
Falling edge of IRQ1, TMIC pin input is detected
Rising edge of IRQ1, TMIC pin input is detected
IRQ2 edge select
0
1
Falling edge of IRQ2 pin input is detected
Rising edge of IRQ2 pin input is detected
IRQ3 edge select
0
1
Falling edge of IRQ3, TMIF pin input is detected
Rising edge of IRQ3, TMIF pin input is detected
IRQ4 edge select
0
1
Falling edge of IRQ4 pin and ADTRG pin is detected
3. Rising edge of IRQ4 pin and ADTRG pin is detected
465
ETC [ ETC ]
