SYSCR1—System control register 1
H'F0
System control
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
LSON
0
2
—
1
1
0
MA1
1
MA0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Active (medium-speed)
mode clock select
0 0 øosc /16
1
1 0
1
øosc /32
øosc /64
øosc/128
Low speed on flag
0
1
The CPU operates on the system clock (ø)
The CPU operates on the subclock (øSUB
)
Standby timer select 2 to 0
0
0
0
1
0
1
Wait time = 8,192 states
Wait time = 16,384 states
Wait time = 32,768 states
Wait time = 65,536 states
Wait time = 131,072 states
Wait time = 2 states
1
0 0
1
1
1 0
1
Wait time = 8 states
Wait time = 16 states
Software standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
463
ETC [ ETC ]
