TMG—Timer mode register G
H'BC
Timer G
Bit
7
OVFH
0
6
OVFL
0
5
OVIE
0
4
3
2
1
CKS1
0
0
CKS0
0
IIEGS CCLR1 CCLR0
Initial value
Read/Write
0
0
0
R/(W)* R/(W)*
W
W
W
W
W
W
Clock select
0
0
1
1
0
1
0
1
Internal clock: counting on ø/64
Internal clock: counting on ø/32
Internal clock: counting on ø/2
Internal clock: counting on øw/4
Counter clear
TCG clearing is disabled
0
1
0
1
0
0
1
1
TCG cleared by falling edge of input capture input signal
TCG cleared by rising edge of input capture input signal
TCG cleared by both edges of input capture input signal
Input capture interrupt edge select
0
1
Interrupt generated on rising edge of input capture input signal
Interrupt generated on falling edge of input capture input signal
Timer overflow interrupt enable
TCG overflow interrupt request is disabled
TCG overflow interrupt request is enabled
0
1
Timer overflow flag L
0
Clearing conditions:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when TCG overflows from H'FF to H'00
Timer overflow flag H
0
Clearing conditions:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
444
ETC [ ETC ]
