SCR31—Serial control register 31
H'9A
SCI31
Bit
7
TIE31
0
6
RIE31
0
5
TE31
0
4
3
2
1
0
RE31 MPIE31 TEIE31 CKE311 CKE310
Initial value
Read/Write
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable
Bit 1
Bit 0
CKE311 CKE310 Communication Mode
Description
Clock Source
Internal clock
Internal clock
Internal clock
Reserved (Do not specify this combination)
External clock
External clock
SCK3 Pin Function
I/O port
Serial clock output
Clock output
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
0
0
1
1
0
1
0
1
Clock input
Serial clock input
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (normal receive operation)
[Clearing conditions]
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0
1
Receive operation disabled (RXD pin is I/O port)
Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0
1
Transmit operation disabled (TXD pin is transmit data pin)
Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0
1
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
424
ETC [ ETC ]
