A.3
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A-4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A-3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL+ M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A-4:
I = L = 2, J = K = M = N= 0
From table A-3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A-4:
I = 2, J = K = 1, L = M = N = 0
From table A-3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Table A-3 Number of Cycles in Each Instruction
Execution Status
(instruction cycle)
Instruction fetch
Access Location
On-Chip Memory
2
On-Chip Peripheral Module
SI
—
Branch address read
Stack operation
SJ
SK
SL
SM
SN
Byte data access
Word data access
Internal operation
2 or 3*
—
1
Note:
*
Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
408
ETC [ ETC ]
