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HD6433846XXXH 参数 Datasheet PDF下载

HD6433846XXXH图片预览
型号: HD6433846XXXH
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器\n [Microcontroller ]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 524 页 / 1465 K
品牌: ETC [ ETC ]
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a. Data transfer format  
The general data transfer format in synchronous communication is shown in figure 10-15.  
*
*
Serial  
clock  
LSB  
Bit 0  
MSB  
Bit 7  
Serial  
data  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Don't  
care  
Don't  
care  
8 bits  
One transfer data unit (character or frame)  
Note: High level except in continuous transmission/reception  
Figure 10-15 Data Format in Synchronous Communication  
In synchronous communication, data on the communication line is output from one falling edge of  
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of  
the serial clock.  
One transfer data character begins with the LSB and ends with the MSB. After output of the  
MSB, the communication line retains the MSB state.  
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial  
clock.  
The data transfer format uses a fixed 8-bit data length.  
Parity and multiprocessor bits cannot be added.  
b. Clock  
Either an internal clock generated by the baud rate generator or an external clock input at the  
SCK3x pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM  
in SMR and bits CKE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection.  
When SCI3 operates on an internal clock, the serial clock is output at the SCK3x pin. Eight pulses  
of the serial clock are output in transmission or reception of one character, and when SCI3 is not  
transmitting or receiving, the clock is fixed at the high level.  
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