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HD6433846XXXH 参数 Datasheet PDF下载

HD6433846XXXH图片预览
型号: HD6433846XXXH
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器\n [Microcontroller ]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 524 页 / 1465 K
品牌: ETC [ ETC ]
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Bit 5: Parity enable (PE)  
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception  
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,  
irrespective of the bit 5 setting.  
Bit 5  
PE  
Description  
0
Parity bit addition and checking disabled*2  
Parity bit addition and checking enabled*1/*2  
(initial value)  
1
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit  
data before it is sent, and the received parity bit is checked against the parity  
designated by bit PM.  
2. For the case where 5-bit data is selected, see table 10-11.  
Bit 4: Parity mode (PM)  
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit  
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and  
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity  
bit addition and checking is disabled.  
Bit 4  
PM  
Description  
Even parity*1  
Odd parity*2  
0
(initial value)  
1
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total  
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,  
a check is carried out to confirm that the number of 1 bits in the receive data plus the  
parity bit is an even number.  
2. When odd parity is selected, a parity bit is added in transmission so that the total  
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a  
check is carried out to confirm that the number of 1 bits in the receive data plus the  
parity bit is an odd number.  
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