Bits 7 to 5: Clock output select (TMA7 to TMA5)
Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock
divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz or 38.4
kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive
mode. øw is output in all modes except the reset state.
CWOSR TMA
Bit 7
Bit 6
Bit 5
CWOS
TMA7
TMA6
TMA5
Clock Output
ø/32
0
0
1
*
0
1
0
1
*
0
1
0
1
0
1
0
1
*
(initial value)
ø/16
ø/8
ø/4
øW/32
øW/16
øW/8
øW/4
1
øW
*: Don’t care
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 1, and cannot be modified.
184
ETC [ ETC ]
