RTL8100C & RTL8100CL
Datasheet
7.10. Rx Decapsulation
The RTL8100C(L) continuously monitors the network when reception is enabled. When activity is
recognized it starts to process the incoming data.
After detecting receive activity on the line, the RTL8100C(L) starts to process the preamble bytes based on
the mode of operation.
While operating in 100Base-TX mode, the RTL8100C(L) expects the frame to start with the symbol pair JK
in the first byte of the 8-byte preamble.
The RTL8100C(L) checks the CRC bytes and checks whether the packet data ends with the TR symbol
pair. If not, the RTL8100C(L) reports an RSR CRC error.
The RTL8100C(L) reports an RSR CRC error in 100Base-TX mode if an invalid symbol (4B/5B Table) is
received in the middle of the frame. The RSR<ISR> bit also sets.
7.11. Flow Control
The RTL8100C(L) supports IEEE 802.3X flow control for improved performance in full-duplex mode. It
detects PAUSE packets to achieve flow control tasks.
7.11.1. Control Frame Transmission
When the RTL8100C(L) detects that its free receive buffer is less than 3K bytes, it sends a PAUSE packet
with pause_time (=FFFFh) to inform the source station to stop transmission for the specified period of time.
After the driver has processed the packets in the receive buffer and updated the boundary pointer, the
RTL8100C(L) sends another PAUSE packet with pause_time (=0000h) to wake up the source station to
restart transmission.
7.11.2. Control Frame Reception
The RTL8100C(L) enters a backoff state for a specified period of time when it receives a valid PAUSE
packet with pause_time (=n). If the PAUSE packet is received while the RTL8100C(L) is transmitting, the
RTL8100C(L) starts to back off after the current transmission completes. The RTL8100C(L) is free to
transmit the next packet when it receives a valid PAUSE packet with pause_time (=0000h) or the backoff
timer (=n*512 bit time) elapses.
Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. PAUSE
packet). NWay flow control capability can be disabled. Refer to section 5.37 EEPROM (93C46) Contents,
page 35.
Single-Chip Fast Ethernet Controller
51
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
