RTL8100C & RTL8100CL
Datasheet
7.5. Line Quality Monitor
The line quality monitor function is available in 100Base-TX mode. It is possible to determine the amount
of Equalization being used by accessing certain test registers with the DSP engine. This provides a crude
indication of connected cable length. This function allows for a quick and simple verification of the line
quality in that any significant deviation from an expected register value (based on a known cable length)
would indicate that the signal quality has deviated from the expected nominal case.
7.6. Clock Recovery Module
The Clock Recovery Module (CRM) is supported in 100Base-TX mode. The CRM accepts 125Mbps
MLT-3 data from the equalizer. The DPLL locks onto the 125Mbps data stream and extracts a 125MHz
recovered clock. The extracted and synchronized clock and data are used as required by the synchronous
receive operations.
7.7. Loopback Operation
Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function
correctly. In loopback mode for 100Mbps, the RTL8100C(L) takes frames from the transmit descriptor and
transmits them up to internal Twister logic.
7.8. Tx Encapsulation
While operating in 100Base-TX mode, the RTL8100C(L) encapsulates the frames that it transmits
according to the 4B/5B code-groups table. The changes to the original packet data are listed below:
1. The first byte of the preamble in the MAC frame is replaced with the JK symbol pair.
2. After the CRC, the TR symbol pair is inserted.
7.9. Collision
If the RTL8100C(L) is not in full-duplex mode, a collision event occurs when the receive input is not idle
while the RTL8100C(L) transmits. If the collision was detected during the preamble transmission, a jam
pattern is transmitted after completing the preamble (including the JK symbol pair).
Single-Chip Fast Ethernet Controller
50
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
