RTL8100C & RTL8100CL
Datasheet
3. Block Diagram
MAC
EEPROM
Interface
LED Driver
Power Control Logic
Early Interrupt
Threshold
Register
Interrupt
Control
Logic
Early Interrupt
Control Logic
PCI
Interface
Transmit/
Receive
Logic
FIFO
Control
Logic
FIFO
MII
Interface
Interface
PHY
100M
5B 4B
Decoder
Data
Alignment
RXD
RXC 25M
Descrambler
10/100
half/full
Switch
Logic
MII
Interface
TXD
TXC 25M
4B 5B
Encoder
Scrambler
10/100M Auto-negotiation
Control Logic
Link Pulse
10M
TXC10
TXD10
Manchester Coded
Waveform
10M Output Waveform
Shaping
RXC10
RXD10
Data Recovery
Receive Low Pass Filter
Transceiver
TD+
TXC 25M
TXD
3 Level
Driver
TXO+
TXO -
Parrallel
to Serial
Variable Current
Baseline
Wander
Correction
Peak
Detect
RXIN+
RXIN-
MLT-3
to NRZI
3 Level
Comparator
Adaptive
Equalizer
ck
Data
RXC 25M
RXD
Serial to
Parrallel
Master
PPL
Slave
PLL
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip Fast Ethernet Controller
3
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
