The interleaver must recover the block boundaries, and the SSTARTIN
pin indicates them by internal strobes; it also resets the interleaver
sequence. You can program the interleaver so that all data fed into the
interleaver RAM before the very first arrival of a SSTARTIN negative
slope is set to zero. This eases operation verification and debugging
during development when the interleaver RAM is completely initialized
with zero values. You must apply a fresh reset to feed zeros after an
active SSTARTIN slope.
The interleaver and the deinterleaver, in sequence, output the original
byte stream after a delay of
Delay = (B – 1) × B × M
In the L64777, the Delay = (11 x 12 x 17) = 2244 clock cycles. Thus, the
delay from the time of the first input byte to the first valid output byte in
the maximum delay path of the interleaver is half of this value, which is
1122 valid clock cycles.
If the QAM is not in 256 mode, the interleaver inserts invalid cycles in an
eight-byte sequence, which proportionally increases the delay time. The
zero delay path in the interleaver delivers data with a propagation delay
of three clock cycles. This is equal to the delay of the interleaver when
it is off.
2.9 Bytes to M-tuples Converter
This unit cuts down bytes to slices of m = 1, 2, 3, 4, 5, 6, 7, and 8 bits.
The programming parameter, mSize (see Section 4.1.2, “Register 1,”
page 4-4), must be set to m − 1. The order is the MSB of the oldest byte
first. See the Digital Broadcasting Systems for Television Sound and
Data Services: Framing Structure, Channel Coding and Modulation
Cable Systems for a detailed specification. When cutting six-bit symbols,
it cuts three bytes into four symbols. The case of four-bit symbols is trivial
(eight bits are split into two sets of four bits each).
Figure 2.16 outlines the basic principle for symbol cutting out of bytes.
Modes for m = 5 and m = 7 are similar.
2-24
Modulator Architecture
ETC [ ETC ]
