Functional Description
4.6
Data Integrity Support
The 82443BX supports ECC (Error Checking and Correcting) or EC (Error Checking) data
integrity modes on the 64-bit DRAM interface. The Intel® 440BX AGPset does not support the
Pentium‚ Pro processor bus ECC protection. This mechanism is defined in the context of the
Pentium Pro processor bus specification to support building of mission critical fault-tolerant
systems. The ECC generation capability is essential for the high-end multiprocessor platforms
where robustness of the system depends on the complexity of the routing of the Pentium Pro
processor bus signals and operational bus frequency. UP/DP platforms based on the Intel® 440BX
AGPset do not have the same requirements and therefore, the 82443BX does not support Pentium
Pro processor bus ECC. Both the EC mode and the ECC mode are supported with either SDRAM
or EDO DRAM.
4.6.1
Data Integrity Mode Selection
The 82443BX supports three modes of data integrity on the memory interface.
• No ECC with Byte-wise write support
• EC Mode (Error Checking only, no correction)
• ECC Mode (Error Checking and Correcting)
These modes are selected via the DRAM Data Integrity Mode (DDIM) field in the NBXCFG
register.
4.6.1.1
4.6.1.2
Non-ECC (Default Mode of Operation)
After CPURST#, the 82443BX ECC control logic is set in the default mode, no data integ-
rity or Non-ECC. This is the highest performance mode for the memory interface. Reads
from memory are not delayed for error checking and correcting and writes of less than a
QWord are performed without any overhead.
EC Mode
When the NBXCFG Register, bits 8:7 (DDIM) are set to 01, the 82443BX DRAM Controller is in
EC mode. In this mode, the 82443BX external signals MECC[7:0] are driven with a protection
code on writes and are checked with an internally generated code on reads. Writes of less than a
QWord are performed as read-merge-write operations.
In EC mode, the 82443BX checks for errors on reads; however, it does not correct the data that is
returned to the requesting agent. Also memory scrubbing is not performed. Note that the ECC code
always protects or covers an entire QWord of data. When a write of less than a QWord is initiated,
the QWord which is targeted by the write must be read, the new write data merged and the entire
new QWord must then be written back to memory. Partial writes (writes of less than a QWord) are
slowed since this read-merge-write operation is required.
4.6.1.3
ECC Mode
Selection between ECC and EC mode is performed entirely by software. If the system designer
decides to select ECC protection for the 72-bit memory array (64bit memory data bus plus 8 ECC
check bits), then MECC[7:0] signals carry ECC information to the 82443BX. The 82443BX
generates/checks ECC as described in detail the following sections.
82443BX Host Bridge Datasheet
4-25
ETC [ ETC ]
