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FW82443BX 参数 Datasheet PDF下载

FW82443BX图片预览
型号: FW82443BX
PDF下载: 下载PDF文件 查看货源
内容描述: 控制器杂项 - 数据表参考\n [Controller Miscellaneous - Datasheet Reference ]
分类和应用: 控制器
文件页数/大小: 132 页 / 642 K
品牌: ETC [ ETC ]
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Functional Description  
Figure 4-5. Three-SODIMMs SDRAM Configuration  
82443BX  
CSA[1:0]#  
CSA[3:2]#  
CSA[5:4]#  
SRASA#  
SCASA#  
DQMA[7:0]#  
WEA#  
MAB[13:11#, 10, 9:0#]  
MD[63:0]  
MECC[7:0]  
CKE[1:0]  
CKE[3:2]  
CKE[5:4]  
SRASB#  
SCASB#  
WE_B#  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
SODIMM2 SODIMM1 SODIMM0  
CASB[5,1]/DQMB[5:1]#  
MAA[13:0]  
RASB[5:0]/CS_B[5:0]#  
NOTE:  
1. These signals are not used and should be left unconnected.  
4.3.1.1  
Configuration Mechanism For DIMMS  
Detection of the type of DRAM installed on the DIMM is supported via Serial Presence Detect  
mechanism as defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL, SDA  
and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special  
programmable modes are provided on the 82443BX for detecting the size and type of memory  
installed. Type and size detection must be done via the serial presence detection pins.  
Memory Detection and Initialization  
Before any cycles to the memory interface can be supported, the 82443BX DRAM registers must  
be initialized. The 82443BX must be configured for operation with the installed memory types.  
Detection of memory type and size is done via the System Management Bus (SMB) interface on  
the PIIX4E. This two wire bus is used to extract the DRAM type and size information from the  
serial presence detect port on the DRAM DIMMs.  
DRAM DIMMs contain a 5 pin serial presence detect interface, including SCL (serial clock), SDA  
(serial data) and SA[2:0]. Devices on the SMBus bus have a seven bit address. For the DRAM  
DIMMs, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0]  
pins. SCL and SDA are connected directly to the System Management Bus on the PIIX4E. Thus  
data is read from the Serial Presence Detect port on the DIMMs via a series of IO cycles to the  
south bridge. BIOS essentially needs to determine the size and type of memory used for each of the  
eight rows of memory in order to properly configure the 82443BX memory interface.  
82443BX Host Bridge Datasheet  
4-19  
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