Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
Terminating Record
1. Host disables DMA requests from the CT8022 by writing 0000H to the Hardware Control Register.
2. Host writes IDLE = 0000H command or STOP RECORD = 5120H command to the Software Control Register.
3. CT8022 terminates record and clears RX Ready if set (in Hardware Status Register).
4. CT8022 writes status response to Software Status Register.
5. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
Note: After writing the Idle or Stop Record command to terminate recording, the Host/DMA should not
attempt to access the Host Receive Data Buffer Access Port even if the RX Ready bit is set. When
cleaning up at the end of recording, the Host should ensure that any partial frame at the end of the
recording is discarded. When the recorded data is sent back to the CT8022 for playback, the
CT8022 can playback only complete frames. It is recommended that the Host synchronize the
termination of recording with the end of transfer of a complete speech frame. This synchronization
can be achieved by examining the DMA’s transfer count register, or by performing the final speech
data frame transfer using the Host processor.
Example 4: TrueSpeech 8.5 Recording using CT8005/CT8015 protocol via Software Control and Status
Registers.
This example shows how to perform TrueSpeech 8.5 recording with TFR Mode = 00 using the CT8015-compatible
protocol. Data is transferred via the Software Control and Status Registers. The Host processor performs all data
transfers. The example shown uses the CT8015 Poll Sync Mode.
1. CT8022 is in IDLE or PLAYBACK state.
2. Host checks for CONTROL READY state in Hardware Status Register.
3. Host selects TrueSpeech 8.5 recording by writing the Select TrueSpeech Record Rate command = 5130H to the
Software Control Register.
4. CT8022 responds via the Software Status Register
5. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
6. Host selects Poll Sync Mode for record using the command 5102H.
7. CT8022 responds via the Software Status Register.
8. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
9. Host writes Record C1 command = 1C00H (TrueSpeech 8.5) to the Software Control Register.
10. CT8022 activates record mode and performs internal synchronization (1-2 frame delay).
11. CT8022 responds with Record status S1 = 1C00H.
12. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
13. Host sends Record C2 command = 1000H.
14. CT8022 responds with Record S2 status = 10X0H, where X is defined by the PEAK bit state.
15. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022
response from the Software Status Register. This clears the STATUS READY bit.
16. Host sends Record C3 with the number of (16 bit) words it wishes to transfer = 1010H.
17. CT8022 checks number of words ready to transfer.
18. CT8022 responds with Record S3 = 1000H or 1010H. If number of words is not zero DATAFLAG/
signal is asserted to indicate the beginning of data transfer.
19. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022
response from the Software Status Register. This clears the STATUS READY bit.
20. If number of words to transfer is zero (S3 = 1000H), Host goes back to step 13.
21. Optional: Host waits for DATAFLAG/ signal to be asserted
22. Host writes data transfer command = 1000H to Software Control Register
23. CT8022 responds with 16-bit data word in Software Status Register
24. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022
response from the Software Status Register. This clears the STATUS READY bit.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
63
All specifications are subject to change without prior notice.
ETC [ ETC ]
