TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
Example 3: Linear 16-bit Record via Host Receive Data Buffer Access Port - Using DMA
This example shows how to start recording in uncompressed 16-bit Linear Format Speech with data transfers
performed via the Host Receive Data Buffer Access Port. An external DMA controller performs all data transfers in
this example.
Starting Record
1. CT8022 is in IDLE state or PLAYBACK state.
2. Host checks for CONTROL READY state in Hardware Status Register.
3. Host selects Poll Sync Mode for record using the command 5102H.
4. CT8022 responds via the Software Status Register.
5. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
6. Host selects Record by issuing the RECORD C1 command = 1E83H (RECMODE = [binary] 101) via the
Software Control Register. This also informs the CT8022 that data transfers will occur via the Host Receive
Data Buffer Access Port (TFR Mode = [binary] 11 ).
7. CT8022 performs internal synchronization then responds with the RECORD S1 status response after a delay of
up to 2 speech frame periods.
8. Host waits for STATUS READY indication in the Hardware Status Register, then reads the CT8022 response
from the Software Status Register. This clears the STATUS READY bit.
9. Host programs external DMA controller to accept DMA requests from the CT8022 (See DMA Direction bit in
Hardware Control Register). Host configures a data buffer in the Host memory to receive the DMA-ed speech
data. The DMA memory buffer should be an integral multiple of the speech frame size. In the case of
uncompressed 16-bit Linear, this should be N*480 (bytes).
10. Host sets up an ISR to handle an end-of-transfer (EOT) interrupt from the DMA controller when it reaches the
end of the DMA buffer. Alternatively, if the DMA supports circular-buffering (auto-initialize), the Host can
poll the DMA to determine when the end of the buffer is reached.
11. Host programs the Hardware Control Register to generate a DMA request from the CT8022 on the RX Ready
condition by writing 0050H ( RX DMA Burst Mode, RX DMA enable) - or 0150H (RX DMA Burst Mode, RX
DMA enable, DMA Direction bit set).
12. The CT8022 is now in record mode. The CT8022 will produce a uncompressed speech frame every 30ms
(assuming that the base frame size is set to 240). The following sequence occurs between the CT8022 and the
DMA controller to transfer data:
a. CT8022 has 240 word (480 byte) uncompressed 16-bit speech data frame ready for transfer.
b. CT8022 transfers first 16 words into the Host Receive Data Buffer.
c. CT8022 asserts RX Ready.
d. RX Ready drives RXDREQ.
e. DMA controller responds to RXDREQ by asserting RXDACKN.
f. DMA controller performs a burst transfer of 16 words (32 bytes) from the CT8022 to the Host DMA
memory buffer.
g. CT8022 de-asserts RX Ready.
h. CT8022 transfers next 16 words into the Host Receive Data Buffer.
i. CT8022 asserts RX Ready.
j. RX Ready drives RXDREQ.
k. DMA controller responds to RXDREQ by asserting RXDACKN.
l. DMA controller performs a burst transfer of 16 words (32 bytes) from the CT8022 to the Host DMA
memory buffer.
m. CT8022 de-asserts RX Ready.
n. Repeat a-f until all 240 words of the speech data frame have been transferred.
The Host processor also needs to supervise the operation of the DMA controller and arrange for the transfer of the
DMA-ed data to its final destination (e.g. transfer to disk). When the DMA controller reaches the end of the DMA
buffer, the Host must process the data (transfer data to disk). The Host can arrange to receive an EOT interrupt from
the DMA controller, or it can periodically poll the DMA’s internal transfer count register to determine the status of
the DMA.
62
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
