Version: 1.18
Width:
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
0:
1:
selects 8-bit A-law or µ-law CODEC
selects 16-bit linear CODEC
Law:
0:
1:
selects external µ-law CODEC
selects external A-law CODEC
(also affects µ-law/A-law selection of RECMODE and PLAYMODE)
Master:
0:
1:
selects slave mode (FSYNC and SCLK are inputs - default after reset)
selects master mode (FSYNC and SCLK are outputs)
Long:
0:
1:
selects short frame sync mode when WIDE=0
selects long frame sync mode when WIDE=1
OUTPUT CODEC:
00:
01:
10:
11:
default output CODEC routing (playback to CODEC 1)
output signal goes to CODEC 1 only
output signal goes to CODEC 0 only
output signal goes to both CODEC 0 and CODEC 1
INPUT CODEC:
Set Rate:
0:
1:
normal input CODEC routing (record from CODEC 1)
input from CODEC 0 and CODEC 1 are exchanged (record from CODEC 0)
0:
1:
no action
next command word programs CODEC sample rate dividers
CO_RATE:
This field sets the division factor used to divide the main 45.056 MHz CT8022 clock to
generate SCLK. Division factor is (CO_RATE+1). For example, 45.056 MHz/(21+1) =
2.048 MHz SCLK. The 45.056 MHz main clock is normally generated by the x11 PLL
from an external 4.096 MHz crystal or clock input. CO_RATE must be greater than 4
(master mode only).
FSYNC_RATE:
WIDE:
This field sets the division factor used to divide the SCLK clock to generate FSYNC.
Division factor is (FSYNC_RATE+1). For example, 2.048 MHz/(255+1) = 8.0 KHz.
F_SYNC_RATE must be greater than 17 (master mode only).
0:
1:
FSYNC is 1 SCLK period wide
FSYNC is 8 SCLK periods wide if Width=0 or 16 SCLK periods wide if
Width=1.
Note that setting the WIDE bit to 1 only has an effect if the LONG bit is
also set.
Before entering Standalone Speakerphone mode, Output CODEC must be set to 00 and Input CODEC set
to 0.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
53
All specifications are subject to change without prior notice.
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