Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
9.2
Basic Protocol
The Host controls the CT8022 via a command-response protocol. For each command the Host writes to the
CT8022, the CT8022 will generate a status response. The Host should read the response before issuing the next
command.
Commands are written to the CT8022 via the Software Control Register (SCR). The CONTROL READY bit in the
Hardware Status Register (HSR) is set to indicate that the CT8022 is ready to accept a command. The Host should
only write to the Software Control Register when the CONTROL READY bit is set. The CT8022 will respond to
the command by writing a status response to the Software Status Register (SSR). The Host should wait for the
STATUS READY bit in the Hardware Status Register to be set before reading from the Software Status Register.
Reading from the Software Status Register will clear the STATUS READY bit.
Commands to the CT8022 always result in an acknowledgment via the Software Status Register. The CT8022
registers are 16-bit. The Host accesses these registers using two 8-bit cycles: low byte and then high byte.
The response time for most commands is usually in the 5-10 microsecond range. However there are a small number
of commands with significantly longer response times of up to 50-60 milliseconds. Notable examples of this are the
commands for starting playback and record, where the command delays its response in order to synchronize with the
internal speech frame period. Detailed information is provided with the individual command descriptions.
Note: Actual command value constants are presented in expanded 16-bit binary form, and also where
appropriate in hexadecimal form with the X value used to indicate user-selected values. For example,
the command 10XXH indicates that the base command is hexadecimal 1000H, but that the least
significant eight bits of the 16-bit command are user-selected, depending on the command options
desired.
9.3
Reset & Start-up Sequence
After Reset, the CT8022 performs internal initialization operations and then sets the CONTROL READY bit in the
Hardware Status Register. The Host should wait for this bit to be set before issuing the first command. After
initialization, the CT8022 enters IDLE mode and awaits a command from the Host. The Host should program the
CODEC configuration before attempting further operations.
Operating Start-up Sequence:
1. Power-on or Reset
2. Host polls Hardware Status Register and waits for CONTROL READY indication.
3. Host writes first command (IDLE = 0000H) to Software Control Register.
4. CT8022 generates command response (0000H) and sets STATUS READY.
5. Host waits for STATUS READY then reads response from Software Status Register.
6. Host writes CODEC configuration command(s) to Software Control Register
7. CT8022 configures the CODEC (master/slave, A-law/µ-law/16-bit and sample rate) and generates a status
response.
8. Host waits for STATUS READY then reads response from Software Status Register.
Optional:
9. Host writes Get Device Identification Code = 3400H to the Software Control Register.
10. CT8022 responds with device code = 8021H and sets STATUS READY.
11. Host waits for STATUS READY then reads response from Software Status Register.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
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All specifications are subject to change without prior notice.
ETC [ ETC ]
