Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
This section contains a list of the CT8022 pins:
Note: The CT8022 is a CMOS device. It is important to make sure that all input pins are connected and
have a valid logic level present at all times. Where noted, certain input pins may require external
pull-up or pull-down resistors.
Signal naming convention: Active low signals are indicated by a trailing “/” or “N” in the signal name as, for
example, SRAMCS/ or SRAMCSN.
Pin Names
HSTDB0
Pin Nrs
Type
I/O/Z
Function
103
106
107
108
109
112
113
114
115
Host Data Bus. HSTDB0 is the least significant data bit.
HSTDB1
HSTDB2
HSTDB3
HSTDB4
HSTDB5
HSTDB6
HSTDB7
HSTAB0
I
I
HSTAB0 is the least significant Host Address bit. It selects between the high and low
byte of the Host interface register selected by HSTAB3-1.
Host Address Bus. These address bits are used to select Host interface register
addressed by Host (in conjunction with HSTCS/).
HSTAB1
HSTAB2
HSTAB3
HSTRD/
116
117
118
122
I
I
I
Host Read signal. Active Low, output enables HSTDB pins, allowing Host to read from
the selected Host interface register. The interface register is selected via a decode of
HSTAB1-3 if HSTCS/ is active, or the Host Receive Data Buffer access port is
selected directly if RXDACK/ is asserted.
Host Write signal. Active Low, clocks data from HSTDB pins into selected Host
interface register. The interface register is selected via a decode of HSTAB1-3 if
HSTCS/ is active, or the Host Transmit Data Buffer access port is selected directly if
TXDACK/ is asserted.
Host Interface Chip Select. Active Low. This signal gates the HSTWR/ and HSTRD/
and HSTAB3-0 address decode during a Host processor access cycle. The
HSTAB3-0 signals should be stable and valid when HSTCS/ is asserted.
This signal must not be asserted during a DMA cycle on the Host port. HSTCS/
must be high when either TXDACK/ or RXDACK/ are asserted (low).
Active High signal. DMA transmit request. This signal is asserted to indicate that the
device is ready to accept transmit data. Data can be transferred by either DMA or a
Host processor access cycle. The Host can enable or disable this signal via the
Hardware Control Register. By default, this signal is disabled.
Active Low signal. DMA Transmit Acknowledge. This signal is asserted by an external
DMA controller on the Host port, together with HSTWR/, to clock a byte from the
HSTDB data bus pins into the Host interface Transmit Data Buffer Access port. This
signal provides direct access to the Host Transmit Data Buffer Access Port, without
involving HSTAB0-3 or HSTCS/. If this signal is not used, it should be connected to
VCC via a 10KOhm pull-up resistor. This signal must not be asserted when either
RXDACK/ or HSTCS/ are active.
(HSTRDN)
HSTWR/
123
124
(HSTWRN)
HSTCS/
(HSTCSN)
TXDREQ
127
128
O
I
TXDACK/
(TXDACKN)
RXDREQ
1
2
O
I
Active High signal. DMA receive request. This signal is asserted to indicate that the
device is ready to provide receive data. Data can be transferred by either DMA or a
Host processor access cycle. The Host can enable or disable this signal via the
Hardware Control Register. By default, this signal is disabled.
Active Low signal. DMA Receive Acknowledge. This signal is asserted by an external
DMA controller on the Host port, together with HSTRD/, to accept a receive data byte
via the HSTDB data bus pins from the Host interface Receive Data Buffer Access port.
This signal provides direct access to the Host Receive Data Buffer Access Port,
without involving HSTAB0-3 or HSTCS/. If this signal is not used, it should be
connected to VCC via a 10KOhm pull-up resistor. This signal must not be asserted
when either TXDACK/ or HSTCS/ are active.
RXDACK/
(RXDACKN)
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
11
All specifications are subject to change without prior notice.
ETC [ ETC ]
