R
XC5200 Series Field Programmable Gate Arrays
carry out
A3
or
B3
CO
DI
DO
D
Q
FD
carry3
DI
CO
DO
D
F4
F3
F2
F1
Q
FD
A3 and B3
to any two
F4
F3
F2
F1
CY_MUX
XOR
XOR
X
sum3
X half sum3
LC3
A2
or
B2
DI
LC3
DI
DO
DO carry2
D
Q
FD
D
F4
F3
F2
F1
Q
FD
A2 and B2
to any two
F4
F3
F2
F1
CY_MUX
XOR
X
half sum2
XOR
X
sum2
LC2
A1
or
B1
DI
LC2
DI
DO
DO carry1
D
Q
FD
D
F4
F3
F2
F1
Q
FD
A1 and B1
to any two
F4
F3
F2
F1
CY_MUX
XOR
X
half sum1
XOR
X
sum1
LC1
A0
or
B0
DI
LC1
carry0
DI
DO
DO
D
Q
FD
D
F4
F3
F2
F1
Q
FD
A0 and B0
to any two
F4
F3
F2
F1
CY_MUX
XOR
X
CI
CE CK
CLR
half sum0
XOR
X
CI
CE CK
CLR
sum0
LC0
LC0
0
carry in
CY_MUX
F=0
Initialization of
carry chain (One Logic Cell)
X5709
Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate
Carry Function
The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A carry multiplexer (CY_MUX) sym-
bol is used to indicate the XC5200 carry logic. This symbol
represents the dedicated 2:1 multiplexer in each LC that
performs the one-bit high-speed carry propagate per logic
cell (four bits per CLB).
While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic func-
tion.
represents an example of an adder function.
The carry propagate is performed on the CLB shown,
which also generates the half-sum for the four-bit adder. An
adjacent CLB is responsible for XORing the half-sum with
the corresponding carry-out. Thus an adder or counter
requires two LCs per bit. Notice that the carry chain
requires an initialization stage, which the XC5200 family
accomplishes using the carry initialize (CY_INIT) macro
and one additional LC. The carry chain can propagate ver-
tically up a column of CLBs.
The XC5200 library contains a set of Relationally-Placed
Macros (RPMs) and arithmetic functions designed to take
advantage of the dedicated carry logic. Using and modify-
ing these macros makes it much easier to implement cus-
7-88
November 5, 1998 (Version 5.2)
ETC [ ETC ]
