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XC5200 Series Field Programmable Gate Arrays
XC5200 Family Compared to
XC4000/Spartan™ and XC3000
Series
For readers already familiar with the XC4000/Spartan and
XC3000 FPGA Families, this section describes significant
differences between them and the XC5200 family. Unless
otherwise indicated, comparisons refer to both
XC4000/Spartan and XC3000 devices.
Table 2: Xilinx Field-Programmable Gate Array
Families
Parameter
CLB function
generators
CLB inputs
CLB outputs
Global buffers
User RAM
Edge decoders
Cascade chain
Fast carry logic
Internal 3-state
Boundary scan
Slew-rate control
XC5200 Spartan XC4000 XC3000
4
20
12
4
no
no
yes
yes
yes
yes
yes
3
9
4
8
yes
no
no
yes
yes
yes
yes
3
9
4
8
yes
yes
no
yes
yes
yes
yes
2
5
2
2
no
no
no
no
yes
no
yes
Configurable Logic Block (CLB) Resources
Each XC5200 CLB contains four independent 4-input func-
tion generators and four registers, which are configured as
four independent Logic Cells™ (LCs). The registers in each
XC5200 LC are optionally configurable as edge-triggered
D-type flip-flops or as transparent level-sensitive latches.
The XC5200 CLB includes dedicated carry logic that pro-
vides fast arithmetic carry capability. The dedicated carry
logic may also be used to cascade function generators for
implementing wide arithmetic functions.
XC4000 family:
XC5200 devices have no wide edge
decoders. Wide decoders are implemented using cascade
logic. Although sacrificing speed for some designs, lack of
wide edge decoders reduces the die area and hence cost
of the XC5200.
XC4000/Spartan family:
XC5200 dedicated carry logic
differs from that of the XC4000/Spartan family in that the
sum is generated in an additional function generator in the
adjacent column. This design reduces XC5200 die size and
hence cost for many applications. Note, however, that a
loadable up/down counter requires the same number of
function generators in both families. XC3000 has no dedi-
cated carry.
XC4000/Spartan family:
XC5200 lookup tables are opti-
mized for cost and hence cannot implement RAM.
Routing Resources
The XC5200 family provides a flexible coupling of logic and
local routing resources called the VersaBlock. The XC5200
VersaBlock element includes the CLB, a Local Interconnect
Matrix (LIM), and direct connects to neighboring Versa-
Blocks.
The XC5200 provides four global buffers for clocking or
high-fanout control signals. Each buffer may be sourced by
means of its dedicated pad or from any internal source.
Each XC5200 TBUF can drive up to two horizontal and two
vertical Longlines. There are no internal pull-ups for
XC5200 Longlines.
Input/Output Block (IOB) Resources
The XC5200 family maintains footprint compatibility with
the XC4000 family, but not with the XC3000 family.
To minimize cost and maximize the number of I/O per Logic
Cell, the XC5200 I/O does not include flip-flops or latches.
For high performance paths, the XC5200 family provides
direct connections from each IOB to the registers in the
adjacent CLB in order to emulate IOB registers.
Each XC5200 I/O Pin provides a programmable delay ele-
ment to control input set-up time. This element can be used
to avoid potential hold-time problems. Each XC5200 I/O
Pin is capable of 8-mA source and sink currents.
IEEE 1149.1-type boundary scan is supported in each
XC5200 I/O.
Configuration and Readback
The XC5200 supports a new configuration mode called
Express mode.
XC4000/Spartan family:
The XC5200 family provides a
global reset but not a global set.
XC5200 devices use a different configuration process than
that of the XC3000 family, but use the same process as the
XC4000 and Spartan families.
XC3000 family:
Although their configuration processes dif-
fer, XC5200 devices may be used in daisy chains with
XC3000 devices.
XC3000 family:
The XC5200 PROGRAM pin is a sin-
gle-function input pin that overrides all other inputs. The
PROGRAM pin does not exist in XC3000.
7-84
November 5, 1998 (Version 5.2)
ETC [ ETC ]
