NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Block Diagram (32Mb x 4)
CKEn
CK
QFC
generator
QFC
(Optional)
DRVR
CK
CSn
WE
CAS
RAS
Bank3
Bank2
Bank1
Clk
DLL
Mode
Registers
12
4096
Bank0
Memory
Array
12
Data
1
(4096 x 1024 x 8)
4
4
4
8
Sense Amplifiers
DQS
Generator
DQ0-DQ3,
DM
COLo
Mask
DQS
Input
I/O Gating
DM Mask Logic
8
Register
2
DQS
A0-A11,
BA0, BA1
1
1
Write
14
1
4
FIFO
1
1
&
8
2
8
2
1024
(x8)
Drivers
4
4
4
4
clk clk
Column
Decoder
in
out
Data
10
1
COLo
Clk
Column-Address
Counter/Latch
11
COLo
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
5
REV 1.0
May, 2001
©
NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
ETC [ ETC ]
