NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
CAS Latency = 2
CK
CK
Read
Read
BAa, COL x
CL=2
Read
Read
NOP
NOP
Command
Address
BAa, COL n
BAa, COL b
BAa, COL g
DQS
DQ
DOa-n
DOa-n'
DOa-x
DOa-x'
DOa-b
DOa-b’
DOa-g
CAS Latency = 2.5
CK
CK
Read
Read
Read
Read
NOP
NOP
Command
Address
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
CL=2.5
DQS
DQ
DOa-n
DOa-n'
DOa-x
DOa-x'
DOa-b
DOa-b’
DO a-n, etc. = data out from bank a, column n etc.
n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).
Don’ t Care
Reads are to active rows in any banks.
Shown with nominal t , t
, and t
.
AC DQSCK
DQSQ
24
REV 1.0
May, 2001
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NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
ETC [ ETC ]
