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EP1K100 参数 Datasheet PDF下载

EP1K100图片预览
型号: EP1K100
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件
文件页数/大小: 86 页 / 915 K
品牌: ETC [ ETC ]
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ACEX 1K Programmable Logic Device Family Data Sheet
Table 5
shows ACEX 1K device performance for more complex designs.
These designs are available as Altera MegaCore
TM
functions.
Table 5. ACEX 1K Device Performance for Complex Designs
Application
LEs
-1
16-bit, 8-tap parallel finite impulse response (FIR)
filter
8-bit, 512-point Fast Fourier transform (FFT)
function
a16450
universal asynchronous
receiver/transmitter (UART)
597
1,854
342
192
23.4
113
36
Performance
Speed Grade
-2
156
28.7
92
28
Units
-3
116
38.9
68
20.5
MSPS
µ
s
MHz
MHz
Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlaster
TM
, ByteBlasterMV
TM
, or BitBlaster
TM
download cables.
After an ACEX 1K device has been configured, it can be reconfigured in-
circuit by resetting the device and loading new data. Because
reconfiguration requires less than 40 ms, real-time changes can be made
during system operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it by writing to a virtual
memory location, simplifying device reconfiguration.
13
Tools
Altera Corporation
5