CXD3018Q/R
§1. CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D0
D1
D18 D19 D20 D21 D22 D23
750ns or more
XLAT
Valid
Registers
• The internal registers are initialized by a reset when XRST = 0.
Note) Be sure to set SQCK to high when XLAT is low.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
Total bit length
8 bits
0 to 2
3
8 to 24 bits
8 bits
4 to 6
7
8
20 bits
28 bits
9
24 bits
A
B
C
D
E
28 bits
16 bits
8 bits
16 bits
20 bits
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