CXA1782CQ/CR
Mirror Circuit
The mirror circuit performs peak and bottom hold after the RFI signal has been amplified.
The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time
constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope
fluctuation.
RF_O
RF
31
30
MIRROR HOLD AMP
0.033µ
29
CP
H
I
PEAK&
BOTTOM
HOLD
× 1.4
× 1
RF_I
G
J
K
MIRROR AMP
LOGIC
20k
MIRROR
COMPARATOR
RF_O
0V
G
(RF_I)
0V
H
(PEAK HOLD)
0V
0V
I
(BOTTOM HOLD)
J
K
(MIRROR HOLD)
H
L
MIRR
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold
signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by
comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when
between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time
constant must be sufficiently large compared with the traverse signal.
In the CXA1782, this mirror output is used only during braking operations, and no external output pin is
attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT
output to the MIRR input of the DSP.
– 21 –
ETC [ ETC ]
