U62H64
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH, A -controlled)
i
tcR
Ai
Addresses Valid
ta(A)
DQi
Previous Data Valid
tv(A)
Output Data Valid
Output
Read Cycle 2 (during Read cycle: W = VIH, G-, E1- or E2-controlled)
tcR
Ai
Addresses Valid
ta(E)
ten(E)
tsu(A)
E1
tdis(E)
tdis(E)
tsu(A)
ta(E)
ten(E)
E2
G
ta(G)
tdis(G)
ten(G)
DQi
High-Z
Output Data Valid
Output
*
tPU
*
tPD
ICC(OP)
ICC(SB)
50 %
50 %
* The same applies to E1
Write Cycle 1 (W-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
E2
W
tsu(E)
tw(W)
tsu(A)
tsu(D)
th(D)
DQi
Input Data Valid
ten(W)
High-Z
Input
tdis(W)
DQi
Output
G
April 20, 2004
7
ZMD [ Zentrum Mikroelektronik Dresden AG ]
