Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
IASCI REGISTER DESCRIPTION
Internal Address/Data Bus
Interrupt Request
1
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Data Register
Ch 1: TDR1
TXA
TXA
0
1
ASCI Transmit Shift Register*
Ch 0: TSR0
ASCI Transmit Shift Register*
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Data FIFO
Ch 1: RDR1
RXA
RTS
RXA
1
0
ASCI Receive Shift Register*
Ch 0: RSR0 (8)
ASCI Receive Shift Register*
Ch 1: RSR1 (8)
ASCI Control Register A
Ch 0: CNTLA0 (8)
ASCI Control Register A
Ch 1: CNTLA1 (8)
ASCI
Control
0
ASCI Control Register B
Ch 0: CNTB0 (8)
ASCI Control Register B
Ch 1: CNTB1 (8)
CTS
CTS
1
0
ASCI Status FIFO
Ch 0
ASCI Status FIFO
Ch 1
DCD
ASCI Status Register
Ch 0: STAT0 (8)
ASCI Status Register
Ch 1: STAT1 (8)
0
ASCI Extension Control Reg.
Ch 0: ASEXT0 (7)
ASCI Extension Control Reg.
Ch 1: ASEXT1 (5)
ASCI Time Constant Low
Ch 0: ASTCOL (8)
ASCI Time Constant Low
Ch 1: ASTCIL (8)
ASCI Time Constant High
Ch 0: ASTCOH (8)
ASCI Time Constant High
Ch 1: ASTCIH (8)
Note: *Not Program
Accessible.
CKA
CKA
0
Baud Rate
Generator 0
φ
1
Baud Rate
Generator 1
Figure 32. ASCI Block Diagram
DS971800401
P R E L I M I N A R Y
1-37
ZILOG [ ZILOG, INC. ]
