Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Notes: All Signals with a preceding front slash, “/” are ac-
tive Low, for example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only). Alternatively, an overslash
may be used to signify active Low, for example WR
Power connections follow conventional descriptions be-
low:
Connection
Power
Circuit
Device
V
V
DD
CC
Ground
GND
V
SS
Bus State Control
Interrupt
Timing
Ø
Generator
CPU
16-bit
/DREQ1
TEND1
Programmable
A18/TOUT
DMACS
(2)
Reload Timers
(2)
TXS
TXA0
Clocked
RXS/CTS1
CKS
Serial I/O
Port
CKA0, /DREQ0
RXA0
Asynchronous
SCI
(Channel 0)
/RTS0
/CTS0
/DCD0
TXA1
CKA1, /TEND0
RXA1
Asynchronous
SCI
(Channel 1)
MMU
VCC
VSS
Address
Buffer
Data
Buffer
A19-A0
D7-D0
Figure 1. Z80180/Z8S180/Z8L180 Functional Block Diagram
1-2
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
