Z8 Encore!® Motor Control Flash MCUs
Product Specification
70
PWM Prescaler
The prescaler allows the PWM clock signal to be decreased by factors of 1, 2, 4, or 8 with
respect to the system clock. The PRES[1:0]bit field in the PWM Control 1 Register
(PWMCTL1) controls prescaler operation. This 2-bit PRESfield is buffered so that the
prescale value only changes upon a PWM reload event.
PWM Period and Count Resolution
The PWM counter operates in two modes to allow edge-aligned outputs and center-
aligned outputs. Figures 8 and 9 illustrate edge- and center-aligned PWM outputs. The
period of the PWM outputs, PERIOD, is determined by which mode the PWM counter is
operating. The active time of a PWM output is determined by the programmed duty cycle,
PWMDC, and the programmed deadband time, PWMDB.
The sections that follow these two figures describe the PWM timer modes and the regis-
ters that control the duty cycle and deadband time.
PWMxH
No Deadband
PWMxL
Period
PWMxH
Deadband Insertion
PWMxL
PWMDB
PWMDB
PWMDC
Figure 8. Edge-Aligned PWM Output
Pulse-Width Modulator
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
