Z8 Encore!® Motor Control Flash MCUs
Product Specification
30
Table 9. Reset Status and Control Register (RSTSCR)
BITS
FIELD
RESET
R/W
7
POR
6
5
4
EXT
3
FLT
2
1
0
STOP
WDT
Reserved
R
FLTSEL
See Table 10 below
R
0
R
R
R
R
R/W
FF0H
ADDR
The FLTSELbit in this register allows software selection of the RESET pin. The pin func-
tion is selected by writing the unlock sequence followed by the mode to this register. A
software write to the FLTSELbit will override the value set by the FLTSELuser option bit.
0 = RESET/Fault0 pin is configured as RESET input.
1= RESET/Fault0 pin is configured as Fault0 input.
Table 10. Reset Status Register Values Following Reset
Reset or Stop-Mode Recovery Event
Power-On Reset
POR
STOP
WDT
EXT
0
FLT
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
Reset using RESET pin assertion
1
0
Reset using Watch-Dog Timer time-out
Reset by OCD writing OCDCTL[0] to 1
Reset from Fault Detect Logic
1
0
1
0
1
1
Stop-Mode Recovery using GPIO pin transition
Stop-Mode Recovery using Watch-Dog Timer time-out
0
0
0
0
Note: Additional bits may be set depending on the number of resets simultaneously occurring.
Reset and Stop-Mode Recovery
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
